1. Field of the Invention
The field of this invention is electronics, and particularly the simulation of electronic circuitry using computer-based simulation tools.
2. Description of the Related Art
A typical integrated circuit (IC) contains thousands of clock paths. A clock path p is a sequence of one or more intermediate cells m that carry a clock signal from a clock source cell to a clock leaf cell. The number of intermediate cells in p is denoted mp. In a typical clock path, mp is 3-30. Each intermediate cell commonly contains 5-20 individual electronic components, e.g., transistors, diodes, etc.
FIG. 1 is a block diagram of a typical clock path 120. Clock path 120 connects clock source cell 110, e.g., a phase-locked loop, to clock leaf cell 130, e.g., a flip-flop. Clock source cell 110 is labeled m=0, and clock leaf cell 130 is labeled m=mp+1, in this case, 5. Clock path 120 comprises four intermediate cells 122, labeled m=1 through m=4=mp. Interconnects 124 connect clock source cell 110, intermediate cells 122, and clock leaf cell 130 to each other. In general, for each intermediate cell m=1 . . . mp−1, the immediately following cell is also an intermediate cell, but, for the last intermediate cell mp, the immediately following cell is the clock leaf cell mp+1.
A clock source cell, such as clock source cell 110 in FIG. 1, transmits a clock signal. A typical clock signal is a periodic alternation between a low voltage value and a high voltage value, i.e., a square wave. A transition from a low voltage value to a high voltage value is a rising-edge transition, and a transition from a high voltage level to a low voltage level is a falling-edge transition. Consecutive transitions of a like kind (e.g., consecutive rising-edge transitions) are consecutively numbered and represented by the variable i. Thus, consecutive rising-edge transitions are numbered i=1, i=2, i=3, etc., and consecutive falling-edge transitions are similarly numbered i=1, i=2, i=3, etc.
The time at which a rising-edge transition i is received at the input of either an intermediate cell m=1 . . . mp in clock path p or clock leaf cell mp+1 is denoted Tr(p,i,m=m-1). Thus, for example, Tr(p,i,m=0) is the time at which rising-edge transition i is received at the input of first intermediate cell m=1, and Tr(p,i,m=mp) is the time at which rising-edge transition i is received at the input of clock leaf cell mp+1. Similarly, the time at which a falling-edge transition i is received at the input of either an intermediate cell m=1 . . . mp in clock path p or clock leaf cell mp+1 is denoted Tf(p,i,m=m-1).
The ideal pulse width PWideal of a clock signal is the duration between the time (e.g., Tr(p,i,m=0)) at which a transition is received at the input of the first intermediate cell m=1 and the time (e.g., Tf(p,i,0)) at which the immediately following transition is received at that same input. The ideal clock cycle Tideal of a clock signal is the duration between the time (e.g., Tr(p,i,m=0)) at which a transition is received at the input of the first intermediate cell m=1 and the time (e.g., Tf(p,i,m=0)) at which the immediately following transition of a similar kind (i.e., falling edge to falling edge or rising edge to rising edge) is received at that same input.
The cell delay Dcr(p,i,m) of intermediate cell m (i.e., the amount of time that it takes for a rising-edge transition i to propagate from the input of intermediate cell m to the input of the immediately following cell m+1) is the difference between Tr(p,i,m) and Tr(p,i,m=m-1). Similarly, the cell delay Dcf(p,i,m) of intermediate cell m (i.e., the amount of time that it takes for a falling-edge transition i to propagate from the input of intermediate cell m to the input of the immediately following cell m+1) is the difference between Tf(p,i,m) and Tf(p,i,m-1).
The clock-path delay DLr(p,i) of rising-edge transition i in clock path p is the sum of cell delays Dcr(p,i,m=1) through Dcr(p,i,m=mp). Similarly, clock-path delay DLf(p,i) for falling-edge transition i in clock path p is the sum of cell delays Dcf(p,i,m=1) through Dcf(p,i,m=mp).
If the clock-path delays of a clock path are constant over time, then the clock signal received at the input of the clock leaf cell mp+1 will possess ideal pulse width PWideal and ideal clock cycle Tideal. Clock-path delays, however, can vary over time due to variations in the delays of one or more intermediate cells in the clock path. One cause of cell-delay variation is change in the intermediate cell's effective power supply voltage Veff,m, defined as the difference between the intermediate cell's high power supply voltage VDD,m and the intermediate cell's low power supply voltage VSS,m. Specifically, higher Veff,m typically results in smaller cell delays, and lower Veff,m typically results in greater cell delays.
Thus, a Veff,m drop or rise between any two transitions will typically cause an increase or decrease in the clock-path delay of clock path p, in turn causing the second transition to transit clock path p in a greater or lesser amount of time than the first transition. In that case, the duration between those two transitions will diverge from an ideal duration. For example, a Veff,m increase between a rising-edge transition and an immediately following falling-edge transition propagating through clock path p may reduce clock-path delay for the second, falling-edge transition. As such, that second transition will transit clock path p in less time than the first transition, causing the duration between those two transitions, i.e., the pulse width, to decrease and thus diverge from PWideal. Similarly, a Veff,m decrease between two consecutive falling-edge transitions may cause the second transition to occur later than ideal and hence cause the duration between those two transitions, i.e., the clock cycle, to increase and diverge from Tideal.
FIG. 2 graphically illustrates the effect of variations in the effective power supply voltage of an intermediate cell m in clock path p on a clock signal transiting that cell. In particular, FIG. 2(a) shows a clock signal as it appears at the input of the first intermediate cell (i.e., m=1) in clock path p, a square wave with ideal pulse width PWideal, ideal clock period Tideal, and transitions at times Tr(p,i=1,m=0) through Tf(p,i=3,m=0). FIG. 2(b) shows variations in Veff,m=1 over time. FIG. 2(c) shows the clock signal received at the input of the immediately following cell, the clock signal's transitions delayed by cell delays Dcr(p,i=1,m=1) through Dcf(p,i=3,m=1), yielding transition times Tr(p,i=1,m=1) through Tf(p,i=3,m=1). Note that maximum Veff,m=1 at time Tr(p,i=1,m=0) results in minimum clock-path delay Dcr(p,i=2,m=1), while minimum Veff,m=1 at time Tr(p,i=1,m=0) results in maximum clock-path delay Dcr(p,i=2,m=1).
An analogous, but different, FIG. 2 could be generated for successive intermediate cells m=2 through m=mp. Those analogous figures would differ from FIG. 2 in that (i) the Veff,m(t) waveform might be different, and, due to the effects of upstream cells, (ii) the duration between a transition and an immediately following transition in the input clock signal would not necessarily the equal ideal pulse width, and (iii) the duration between a transition and an immediately following transition of a similar kind (e.g., rising edge to rising edge or falling edge to falling edge) in the input clock signal would not necessarily equal the ideal clock cycle.
Variation in transition time is called jitter. There are several metrics for quantifying jitter. PWmax and PWmin are, respectively, the maximum and minimum pulse widths. Rising-edge cycle-to-cycle jitter JTr,c2c,i is the absolute value of the difference between (1) the ideal clock cycle Tideal and (2) a clock cycle defined by a rising-edge transition i and the immediately following rising-edge transition i+1. Similarly, falling-edge cycle-to-cycle jitter JTf,c2c,i is the absolute value of the difference between (1) the ideal clock cycle Tideal and (2) a clock cycle defined by a falling-edge transition i and the immediately following falling-edge transition i+1. Maximum rising-edge cycle-to-cycle jitter JTr,c2c,max is the maximum value from a set of rising-edge cycle-to-cycle jitter values, and maximum falling-edge cycle-to-cycle jitter JTf,c2c,max is the maximum value from a set of falling-edge cycle-to-cycle jitter values. Maximum periodic rising-edge jitter JTr,period,max and maximum periodic falling-edge jitter JTf,period, max are the differences between Tideal and a hypothetical clock cycle defined by the most- and least-delayed transitions of a similar kind from among all transitions in a simulation duration.
Excessive levels of jitter in a system can cause that system's bit error rate (BER) to exceed prescribed limits and thus render that system unacceptable. As such, systems are designed to keep jitter within specified limits. Because it is impractical to physically mock-up a billion-element electronic system prior to final manufacture, system designers use simulation software to simulate their system designs and predict system jitter. These simulation programs accept various inputs describing a system—e.g., performance profiles for various components, power supply voltages, length and composition of interconnections, etc.—and return various estimated performance statistics, such as clock-path delay.
One such simulation program, Simulation Program with Integrated Circuit Emphasis (SPICE), can be used to model every single element within a system, e.g., every transistor, every diode, etc. As such, SPICE provides an accurate prediction of system performance, but at a price of time. Modeling a single clock path in SPICE can take from two to seven hours. Thus, modeling the thousands of clock paths in a typical system with SPICE can be impractical.
An alternative modeling tool is Static Timing Analysis (STA) software, e.g., Primetime software from Synopsys Design, Inc. of Mountain View, Calif. STA models not at the element level, but at the cell level, and thus can model the performance of an entire system in a more-reasonable amount of time.
However, unlike SPICE, STA does not model system performance over a period of time, but only calculates a snapshot. Thus, since jitter is defined as variation in transition time over time, calculating clock-path jitter with STA typically involves performing two or more STA simulations.
In a typical method, the first step is to simulate Veff,m for an entire clock path p over a simulation duration. This simulation is typically performed with commercially available system-level power-grid modeling software from companies like Synopsys (Mountain View, Calif.) and Cadence (San Jose, Calif.).
Next, the maximum Veff,m is selected from the simulation results, and STA is used to calculate the clock-path delay of p given that maximum Veff,m. STA assumes that each intermediate cell m in clock path p receives that exact same maximum Veff,m value, and thus the clock-path delay of clock path p will be at minimum. Then, the minimum Veff,m is selected from the simulation results, and a second STA simulation is performed which returns the maximum clock-path delay of clock path p. Last, the maximum and minimum clock-path delays are used as inputs for jitter metric calculations, e.g., minimum and maximum pulse widths, periodic jitter, and cycle-to-cycle jitter.
This prior-art method generates overly pessimistic jitter metrics for two reasons. First, contrary the method's assumption, it is extremely improbable that each and every intermediate cell in a clock path will be at the exact same Veff,m value, maximum or minimum, when it is that cell's turn to process the same transition i. Even if all intermediate cells in a clock path are receiving the same Veff,m value at the same time, it still takes a measurable amount of time for transition i to travel from intermediate cell m to intermediate cell m+1. Thus, even if intermediate cells m and m+1 are both at maximum/minimum Veff,m when intermediate cell m processes transition i, by the time transition i arrives at intermediate cell m+1, the Veff,m of intermediate cell m+1 may have changed, making the maximum cell delay a little smaller, or the minimum cell delay a little larger.
Second, combining minimum and maximum clock-path delays can sometimes ignore the actual behavior of Veff,m. Specifically, physical phenomena such as package inductance and board decoupling capacitance typically prohibit Veff,m from going from maximum to minimum, or vice versa, in less than 10-20 nanoseconds. Thus, in a typical system operating at 1 GHz, it will take 10-20 clock cycles for Veff,m to go from maximum or minimum, or vice versa. In other words, it is extremely improbable that Veff,m, and hence cell delays and clock-path delays, will vary between maximum and minimum in the space of a single pulse width or even a single cycle.
Thus, calculating maximum and minimum pulse width, cycle-to-cycle jitter, and some types of periodic jitter using the method described above is doubly pessimistic because (1) calculated maximum and minimum clock-path delays may be respectively greater or smaller than any clock-path delays encountered by a system in practice, and, (2) in practice, maximum clock-path delay will almost never be followed by minimum clock-path delay, or vice versa, in a single pulse width or clock cycle.